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MC74F112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. CONNECTION DIAGRAM
VCC CD1 CD2 CP2 16 15 14 13 K2 12 J2 11 SD2 10 Q2 9
16 1
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
FASTTM SCHOTTKY TTL
J SUFFIX CERAMIC CASE 620-09
C K DQ CP Q J SD 1 CP1 2 K1 3 J1 4 SD1 5 Q1
S J DQ CP K Q CD 6 Q1 7 Q2 8 GND
16
N SUFFIX PLASTIC CASE 648-08
1
FUNCTION TABLE (Each Half)
Inputs @ tn J L L H H
Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse
Output @ tn + 1 Q Qn L H Qn
16 1
D SUFFIX SOIC CASE 751B-03
K L H L H
ORDERING INFORMATION
MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC
LOGIC SYMBOL
4 3 1 2 J SD J
10 SD
Q
5
11 13
Q
9
CP K Q 6
CP K CD 14 Q 7
12
15 VCC = PIN 16 GND = PIN 8
FAST AND LS TTL DATA 4-45
MC74F112
LOGIC DIAGRAM (one half shown)
Q
Q
CD J CP
SD K
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 -1.0 20 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 VOH VOL IIH Output HIGH Voltage Output LOW Voltage Input HIGH Current 74 2.5 2.7 3.4 3.4 0.35 0.5 20 100 Input LOW Current (J and K Inputs) IIL (CP Inputs) (CD and SD Inputs) IOS ICC Output Short Circuit Current (Note 2) Power Supply Current -60 12 -0.6 -2.4 -3.0 -150 19 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A A mA mA mA mA mA VCC = MAX, VOUT = 0 V VCC = MAX, VCP = 0 V VCC = MAX, VIN = 0.5 V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 20 mA VCC = MIN VCC = 4.50 V VCC = 4.75 V VCC = MIN
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-46
MC74F112
AC CHARACTERISTICS
74F TA = +25C VCC = +5.0 V CL = 50 PF Symbol fmax tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Min 110 2.0 2.0 2.0 2.0 6.5 6.5 6.5 6.5 2.0 2.0 2.0 2.0 7.5 ns 7.5 7.5 ns 7.5 Max 74F TA = 0C to +70C VCC = 5.0 V 10% CL = 50 PF Min Max Unit MHz
AC OPERATING REQUIREMENTS
74F TA = +25C VCC = +5.0 V Symbol ts (H) ts (L) th (H) th (L) tw (H) tw (L) tw (L) trec Parameter Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn CPn Pulse Width, HIGH or LOW CDn or SDn Pulse Width, LOW Recovery Time CDn or SDn to CP Min 4.0 3.0 0 0 4.5 4.5 4.5 4.0 Typ Max 74F TA = 0C to +70C VCC = 5.0 V 10% Min 4.0 3.0 ns 0 0 4.5 ns 4.5 4.5 5.0 ns ns Max Unit
FAST AND LS TTL DATA 4-47

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